Design and Optimization of High-Speed GNRFET Based 9T SRAM Circuit

Abstract

We present a low-leakage graphene nano-ribbon transistor (GNRFET)-based static random-access memory (SRAM) cell in 16nm technology that operates near the subthreshold region. Compared to conventional Si-CMOS technology, our proposed cell improves read stability by 1.92 times and write ability by 3.24 times. HSPICE tool simulations demonstrate that our proposed cell significantly outperforms existing 9T SRAM cells in terms of power consumption, latency, read stability, and write ability. Additionally, at a low supply voltage of 325mV, we employ a multi-threshold approach and transistor optimizations to improve the read static noise margin (RSNM). By utilizing the multi-threshold approach in the write port, the overall power consumption of our proposed cell is reduced by a factor of 4223 compared to a conventional 9T SRAM cell. Device optimization and the multi-threshold approach, which enhance both read and write performance, can significantly minimize read and write delays.