High-Performance of GNRFET Based Ternary Half-Adder and Multiplexer

Abstract

This research introduces a novel ternary half-adder and multiplexer design using graphene nano-ribbon field-effect transistors (GNRFETs). Ternary logic, an alternative to binary logic, offers potential advantages in terms of circuit simplicity and energy efficiency due to reduced overhead. The proposed ternary circuits, particularly when combined with traditional binary logic gates, show promise for data routing applications like half-adders and multiplexers. Extensive simulations using HSPICE indicate significant improvements in power consumption and delay compared to previous GNRFET implementations. The power-delay product is reduced by over 87% when the ternary circuit is integrated with binary gates in practical applications.