Power Aware and Latency Optimized Dma Connected Ddr5 with Clock Gating Using Axi

Abstract

The project aims to design a softcore processor system with Advanced eXtensible Interface (AXI) processor bus which deals with different data capacities with 32-, 64-, 128-, and 256-bits data width. The system deals with Direct Memory Access (DMA) unit to transfer data between the system memory and external peripheral. Memory Controller Block – Dual Data Rate (MCB-DDR5) external memory is introduced to act as main memory system. Registers in DMA controller are designed using general ring counter which consumes more power. As an extension of this concept, ring counter is modified using clock gating technique to reduce power consumption.